1. Field of the Invention
The present invention relates to semiconductor structures, and more particularly, to a method for fabricating a semiconductor structure having an interposer.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip packaging sizes and shorten signal transmission paths and therefore have been widely used for chip packaging. Various types of packages such as chip scale packages (CSPs), direct chip attached (DCA) packages and multi-chip module (MCM) packages can be achieved through flip-chip technologies.
In a flip-chip packaging process, a big CTE (Coefficient of Thermal Expansion) mismatch between a chip and a packaging substrate adversely affects the formation of joints between conductive bumps of the chip and contacts of the packaging substrate, thus easily resulting in delamination of the conductive bumps from the packaging substrate. On the other hand, along with increased integration of integrated circuits, a CIE mismatch between a chip and a packaging substrate induces more thermal stresses and leads to more serious warpage, thereby reducing the product reliability and resulting in failure of a reliability test.
Accordingly, an interposer made of a semiconductor material close to a semiconductor chip has been developed to overcome the above-described drawbacks caused by a CTE mismatch.
FIG. 1A shows a conventional semiconductor package having a through silicon interposer. Referring to FIG. 1A, the semiconductor package has a packaging substrate 9 having a plurality of bonding pads 90 having a large pitch, a semiconductor chip 3 having a plurality of electrode pads 30 having a small pitch, and a through silicon interposer (TSI) 2 disposed between the packaging substrate 9 and the semiconductor chip 3. The through silicon interposer 2 has a substrate unit 20, a plurality of through silicon vias (TSVs) 21 formed in the substrate unit 20 and a redistribution layer (RDL) structure 22 formed on a lower side of the substrate unit 20. The RDL structure 22 of the through silicon interposer 2 is electrically connected to the bonding pads 90 of the packaging substrate 9 through a plurality of conductive elements 23, and the electrode pads 30 of the semiconductor chip 3 are electrically connected to the TSVs 21 through a plurality of solder bumps 31. Further, an underfill 32 is formed between the semiconductor chip 3 and the through silicon interposer 2 to encapsulate the solder bumps 31. In an alternative embodiment, referring to FIG. 1B, an RDL structure 22′ is formed on an upper side of the through silicon interposer 2 on which the semiconductor chip 3 is to be disposed.
The use of the through silicon interposer 2 facilitates to overcome the above-described drawbacks and also reduces the size of the semiconductor package. For example, a flip-chip packaging substrate generally has a minimum line width and pitch of 12 um. When the number of the electrode pads of a semiconductor chip increases, since the line width and pitch of the flip-chip packaging substrate cannot be reduced, the area of the flip-chip packaging substrate must be increased to increase the wiring density so as to accommodate the semiconductor chip having high I/O counts. On the other hand, referring to FIG. 1A, the through silicon interposer 2 can have a minimum line width and pitch of 3 um. Therefore, the semiconductor chip 3 having high I/O counts can be disposed on the through silicon interposer 2 without increasing the area of the packaging substrate 9. As such, the semiconductor chip 3 is electrically connected to the packaging substrate 9 through the through silicon interposer 2.
Further, the through silicon interposer 2 has characteristics of fine pitch and fine line width and therefore facilitates to shorten the electrical transmission path. Therefore, compared with a semiconductor chip directly disposed on a packaging substrate, the semiconductor chip 3 disposed on the through silicon interposer 2 achieves a higher electrical transmission speed.
To fabricate the above-described semiconductor package having the through silicon interposer 2, the through silicon interposer 2 is first bonded to the semiconductor chip 3 to form a semiconductor structure 1 and then the semiconductor structure 1 is disposed on the packaging substrate 9. However, the through silicon interposer 2 is generally comprised of a plurality of substrate units 20. After a plurality of semiconductor chips 3 are bonded to the substrate units 20 of the interposer 2, the overall structure needs to be singulated to obtain a plurality of semiconductor structures 1. Therefore, warpage easily occurs to the through silicon interposer 2 when the semiconductor chips 3 are bonded to the substrate units 20, thereby adversely affecting the electrical connection between the semiconductor chips 3 and the through silicon interposer 2.
Accordingly, referring to FIG. 1B, a carrier 4 having a plurality of concave portions 400 for carrying the interposer has been proposed.
Referring to FIG. 1B, a plurality of concave portions 400 are formed on a surface of a silicon substrate 40 and then a bonding layer 41 made of an adhesive material is formed on the silicon substrate 40 by spin coating. In the present embodiment, the bonding layer 41 is only formed on the surface of the silicon substrate 40. In another embodiment, the bonding layer 41 can be formed not only on the surface of the silicon substrate 40 but also in the concave portions 400 of the silicon substrate 40. Then, the through silicon interposer 2 is attached to the bonding layer 41 with the conductive elements 23 received in the concave portions 400. As such, when the semiconductor chips 3 are disposed on the substrate units 20 of the through silicon interposer 20, the bonding layer 41 facilitates to prevent warping of the through silicon interposer 2 and cracking of the semiconductor chips 3 and ensures a good electrical connection quality between the solder bumps 31 and the through silicon interposer 2.
However, in the above-described method for forming the semiconductor structure 1, different silicon substrates 40 are required according to silicon interposers 2 of different specifications (for example, different numbers and pitches of the conductive elements 23) so as to provide different sizes and numbers of concave portions 400, thus increasing the fabrication cost of the semiconductor package.
Further, the method needs an expensive photoresist material to form the concave portions 400 in the silicon substrate 40. As such, to fabricate different silicon substrates 40, a large amount of the photoresist material is used, thereby greatly increasing the fabrication cost.
Therefore, there is a need to provide a method for fabricating a semiconductor structure so as to overcome the above-described drawbacks.